Modern, high performance, computer systems typically have multiple processors. It is known that some computer systems have primary processors of multiple instruction set types, multiple processor systems having primary processors of multiple instruction set architectures (ISAs) are known herein as heterogeneous computer systems.
Heterogeneous computer systems offer advantages in that they may run application code written for a variety of processor types and operating systems.
In addition to primary processors, upon which operating system and user programs run, there are typically additional embedded processors of additional types. Embedded processors are typically provided for control of specific hardware devices, such as disk drives, in the system. In a computer system, embedded processors may also perform system management functions as monitoring of primary processor voltages and temperatures, control of cooling subsystems, as well as boot-time configuration of various system components.
Machine-language operating system code, including low level system code and BIOS (basic input-output system) code, is ISA specific. For example, machine-level code for a PA8800 will not run correctly on an Intel Itanium processor. In a heterogeneous computer system, each low-level operating system code module typically exists in a separately-compiled module for each primary processor type.
A family of high performance heterogeneous computer systems from Hewlett-Packard can be configured to use primary processors of two or more ISA types, including the Intel Itanium and PA8800 instruction set architectures.
In this family of computer systems, a field replaceable “cell” has several primary processor circuits of the same type, together with memory, circuitry for communicating with other cells over a backplane bus, input output (I/O) bus interface circuitry, JTAG (Joint Test Action Group) scan circuitry, and other circuitry. There may be one or more additional embedded processors in each cell to perform system management functions.
One or more cells, which may, but need not, be of the same type, are installed into a backplane. A heterogeneous computer system is formed when cells having two or more types of processors are inserted into the backplane.
This family of heterogeneous computer systems supports simultaneous execution of multiple operating systems, including multiprocessor variants of Windows-NT, Unix, VMS, and Linux. Multiple instances of each system are also supported. Each operating system instance operates in a partition of the computer system.
At system boot time, a group of processors of a particular type are assigned to operate in each partition. These processors may belong to more than one cell, but must all be of the same ISA. As the operating system instance running in the partition boots, or reinitializes; processors of the partition become aware of each other and appropriate task routing and assignment datastructures built in system memory. The process of processors becoming aware of each other and task routing and assignment datastructures being built in system memory is known herein as a Rendezvous of the processors.
It is known that nonvolatile memory circuits having board identification and timing information may be designed into modules of a computer system. Many Synchronous Dynamic Random Access Memory (SDRAM) modules contain serial memory devices having interface timing information recorded therein. Information in these memory devices is used to configure memory interface circuitry of the computer system such that the system will properly communicate with those memory modules actually installed in the system. The Peripheral Component Interconnect (PCI) bus specification provides for machine-readable identification registers within each peripheral device attached to a PCI bus, information read from these identification registers is typically used by an operating system to allocate bus address space and to determine appropriate drivers for each peripheral device.
Some prior heterogeneous computer systems have assigned processors to partitions according to the physical location of the processors in the system. In these systems, processors on cells installed in particular slots of the backplane are assigned to one partition, those in other slots are assigned to a second partition. Should cells be moved in the backplane, assignment of processors to partitions based on physical location may result in incompatible processors being assigned to a partition.
It is desirable to assign processors to system partitions in a simple, reliable, way. It is desirable to assign processors to partitions in a manner that ensures that each partition includes only compatible processors.